1. Field of the Invention
The present invention relates to a technique for detecting a short-circuit between interconnections of a semiconductor device.
2. Description of the Related Art
In the interconnections of the circuit in a semiconductor device and the like, a short-circuit is generated due to the contact of a conductive foreign matter with an interconnection and the other interconnection. This leads to the defect of a circuit. Even if the circuit is not judged as defective before shipping, there is a possibility that the circuit become defective depending on various conditions.
FIG. 1 is the plane view of a suspected substance. In FIG. 1, a conductive foreign matter 101 exists between a high-voltage interconnection A and a high-voltage interconnection B. The electric potential of the interconnection A and that of the interconnection B may be set in different. In this case, the high-voltage interconnection A and the high-voltage interconnection B are short-circuited through the conductive foreign matter
Therefore, the suspected substance can be judged as being defective in a usual test.
On the other hand, referring to FIG. 2, the conductive foreign matter 102 is placed slightly apart from the high-voltage interconnection A. Therefore, the high-voltage interconnection A and the high-voltage interconnection B are not short-circuited. Therefore, the suspected substance should not be judged as being defective in a usual test. However, a stress and the like after the test may cause the conductive foreign matter 102 to contact the high-voltage interconnection A, and the high-voltage interconnection A and the high-voltage interconnection B will be possibly short-circuited. Such a phenomenon is hereafter referred to as a “short-defect with time passing” or a “latent short-circuit defect.”
A method of applying overvoltage between interconnections has been used in a low-voltage circuit to detect the short-defect with time passing. On the other hand, in the case of a high-voltage circuit, it is necessary to apply higher voltage than the one used in a usual test for detecting the short-defect with time passing by applying overvoltage as well as the low-voltage circuit, and that possibly causes elements to be broken down or deteriorated.
Japanese Laid Open Patent Application (JP-A 2004-14694) as a conventional technique discloses an interconnection test pattern characterized in including at least two resistors the resistance values of which is known on a silicon substrate; an interconnection that connects the resistors electrically in series; an adjacent interconnection formed by the same material as the mentioned interconnection, which is placed adjacent to the interconnection with a predetermined interval; and two terminals that are electrically connected to the mentioned resistors respectively.
Japanese Laid Open Patent Application (JP-A H06-29364) discloses a semiconductor device characterized in including a group of interconnection layers mutually arranged in parallel and a test means that tests whether the mentioned group of interconnection layers is normal or not, wherein the mentioned test means includes; a first potential applying means to apply a first potential to a n-th interconnection layer (n is a multiple of two including 0) in the group of interconnection layers; and a second potential applying means to apply a second potential having at least a different potential from the first potential to n+1-th interconnection layer in the group of interconnection layers, in which, the first potential is applied to the n-th interconnection layer and the second potential is applied to the n+1 interconnection layer at the same time and this status is maintained during a predetermined time.
Japanese Laid Open Patent Application (JP-A H11-23668) discloses an interconnection defect testing circuit as a testing device, which is configured corresponding to an evaluation object circuit and provided on a same substrate as the evaluation object circuit, consisting of a first interconnection and a second interconnection which are electrically insulated, in which a detection circuit forming area for the same evaluation object circuit is divided into a plural, and an insulation-defective detection can be possible in each divided area.